ref: 7328d784f2161757a4413de58e1cb433d0bf3bbe
parent: 2a6e8ef42d269906883ea1b3f1b43dfb13c557a0
author: Roberto E. Vargas Caballero <[email protected]>
date: Sun Sep 22 10:39:20 EDT 2019
[as-powerpc] Add BCLR and BCLRL instructions
--- a/src/cmd/as/as.h
+++ b/src/cmd/as/as.h
@@ -32,6 +32,7 @@
ASTR,
AREG,
ANUMBER,
+ AIMM2,
AIMM3,
AIMM5,
AIMM8,
--- a/src/cmd/as/symbol.c
+++ b/src/cmd/as/symbol.c
@@ -121,6 +121,8 @@
unsigned long long val = np->sym->value;
switch (type) {
+ case AIMM2:
+ return val > 3;
case AIMM3:
return val > 7;
case AIMM5:
--- a/src/cmd/as/target/powerpc/ins.c
+++ b/src/cmd/as/target/powerpc/ins.c
@@ -79,6 +79,7 @@
if ((getclass(np) & class) == 0)
return 0;
break;
+ case AIMM2:
case AIMM5:
case AIMM8:
case AIMM16:
@@ -221,7 +222,20 @@
void
xl_form(Op *op, Node **args)
{
- abort();
+ unsigned long ins, bo, bi, bh, lk;
+ unsigned long opcd1, opcd2;
+ long long dst;
+
+ opcd1 = op->bytes[0];
+ opcd2 = op->bytes[1]<<8 | op->bytes[2];
+ lk = op->bytes[3];
+
+ bo = args[0]->sym->value;
+ bi = args[1]->sym->value;
+ bh = args[2]->sym->value;
+
+ ins = opcd1<<26 | bo<<21 | bi<<16 | bh<<11 | opcd2<<1 | lk;
+ emit_packed(ins);
}
void
--- a/src/cmd/as/target/powerpc/opers.dat
+++ b/src/cmd/as/target/powerpc/opers.dat
@@ -1,3 +1,4 @@
+imm2 AIMM2
imm5 AIMM5
imm8 AIMM8
imm16 AIMM16
--- a/src/cmd/as/target/powerpc/ops.dat
+++ b/src/cmd/as/target/powerpc/ops.dat
@@ -54,3 +54,6 @@
BCL imm5,imm5,imm64 4 16,0,1 b_form POWERPC64
BCLA imm5,imm5,imm32 4 16,1,1 b_form POWERPC
BCLA imm5,imm5,imm64 4 16,1,1 b_form POWERPC64
+
+BCLR imm5,imm5,imm2 4 19,0,16,0 xl_form POWERPC,POWERPC64
+BCLRL imm5,imm5,imm2 4 19,0,16,1 xl_form POWERPC,POWERPC64
--- a/tests/as/execute/powerpc.s
+++ b/tests/as/execute/powerpc.s
@@ -8,3 +8,5 @@
BCL $1,$3,$L2 # 40 23 38 01
L2: BCLA $3,$4,$L2 # 40 64 08 03
+ BCLR $1,$2,$2 # 4C 22 10 20
+ BCLRL $2,$2,$1 # 4C 42 08 21