ref: 031f5756aba3d07939a7eee6b2adf02f0a2d1d8d
parent: 54becb84666114ce76457553fa3f707e4003d322
author: cinap_lenrek <[email protected]>
date: Fri Aug 16 15:24:00 EDT 2019
bcm64: poll gisb arbiter for asynchronous bus errors
--- a/sys/src/9/bcm64/gisb.c
+++ b/sys/src/9/bcm64/gisb.c
@@ -12,46 +12,66 @@
static u32int *regs = (u32int*)(VIRTIO2 + 0x400000);
enum {
+ ArbMasterMask = 0x004/4,
ArbTimer = 0x008/4,
+ TimerFreq = 216000000, // 216MHz
+
ArbErrCapClear = 0x7e4/4,
ArbErrCapAddrHi = 0x7e8/4,
ArbErrCapAddr = 0x7ec/4,
+ ArbErrCapData = 0x7f0/4,
ArbErrCapStatus = 0x7f4/4,
CapStatusTimeout = 1<<12,
CapStatusAbort = 1<<11,
+ CapStatusStrobe = 15<<2,
CapStatusWrite = 1<<1,
CapStatusValid = 1<<0,
ArbErrCapMaster = 0x7f8/4,
+
+ ArbIntrSts = 0x3000/4,
+ ArbIntrSet = 0x3004/4,
+ ArbIntrClr = 0x3008/4,
+
+ ArbCpuMaskSet = 0x3010/4,
};
static int
-arbinterrupt(Ureg *)
+arberror(Ureg*)
{
- u32int status = regs[ArbErrCapStatus];
- u32int master;
+ u32int status, intr;
+ u32int master, data;
uvlong addr;
+ status = regs[ArbErrCapStatus];
if((status & CapStatusValid) == 0)
return 0;
-
+ intr = regs[ArbIntrSts];
master = regs[ArbErrCapMaster];
-
addr = regs[ArbErrCapAddr];
addr |= (uvlong)regs[ArbErrCapAddrHi]<<32;
-
+ data = regs[ArbErrCapData];
+ if(intr)
+ regs[ArbIntrClr] = intr;
regs[ArbErrCapClear] = CapStatusValid;
- iprint("cpu%d: GISB arbiter error: %s%s %s bus addr %llux, master %.8ux\n",
+ iprint("cpu%d: GISB arbiter error: %s%s %s bus addr %llux data %.8ux, "
+ "master %.8ux, status %.8ux, intr %.8ux\n",
m->machno,
(status & CapStatusTimeout) ? "timeout" : "",
(status & CapStatusAbort) ? "abort" : "",
(status & CapStatusWrite) ? "writing" : "reading",
- addr,
- master);
+ addr, data,
+ master, status, intr);
return 1;
}
+static void
+arbclock(void)
+{
+ arberror(nil);
+}
+
void
gisblink(void)
{
@@ -58,6 +78,9 @@
extern int (*buserror)(Ureg*); // trap.c
regs[ArbErrCapClear] = CapStatusValid;
+ regs[ArbIntrClr] = -1;
- buserror = arbinterrupt;
+ addclock0link(arbclock, 100);
+
+ buserror = arberror;
}