ref: 10b456ff446704f32aa2ee237c149244fbabd81d
parent: 811b80cae120168762e5825784a135ee4a5558e2
author: cinap_lenrek <[email protected]>
date: Thu Jul 25 05:01:44 EDT 2019
bcm64: add gisb arbiter driver to catch bus timeouts
--- /dev/null
+++ b/sys/src/9/bcm64/gisb.c
@@ -1,0 +1,63 @@
+#include "u.h"
+#include "../port/lib.h"
+#include "mem.h"
+#include "dat.h"
+#include "fns.h"
+#include "../port/error.h"
+#include "ureg.h"
+
+/*
+ * GISB arbiter registers
+ */
+static u32int *regs = (u32int*)(VIRTIO2 + 0x400000);
+
+enum {+ ArbTimer = 0x008/4,
+ ArbErrCapClear = 0x7e4/4,
+ ArbErrCapAddrHi = 0x7e8/4,
+ ArbErrCapAddr = 0x7ec/4,
+ ArbErrCapStatus = 0x7f4/4,
+ CapStatusTimeout = 1<<12,
+ CapStatusAbort = 1<<11,
+ CapStatusWrite = 1<<1,
+ CapStatusValid = 1<<0,
+ ArbErrCapMaster = 0x7f8/4,
+};
+
+static int
+arbinterrupt(Ureg *)
+{+ u32int status = regs[ArbErrCapStatus];
+ u32int master;
+ uvlong addr;
+
+ if((status & CapStatusValid) == 0)
+ return 0;
+
+ master = regs[ArbErrCapMaster];
+
+ addr = regs[ArbErrCapAddr];
+ addr |= (uvlong)regs[ArbErrCapAddrHi]<<32;
+
+ regs[ArbErrCapClear] = CapStatusValid;
+
+ iprint("cpu%d: GISB arbiter error: %s%s %s bus addr %llux, master %.8ux\n",+ m->machno,
+ (status & CapStatusTimeout) ? "timeout" : "",
+ (status & CapStatusAbort) ? "abort" : "",
+ (status & CapStatusWrite) ? "writing" : "reading",
+ addr,
+ master);
+
+ return 1;
+}
+
+void
+gisblink(void)
+{+ extern int (*buserror)(Ureg*); // trap.c
+
+ regs[ArbErrCapClear] = CapStatusValid;
+
+ buserror = arbinterrupt;
+}
--- a/sys/src/9/bcm64/trap.c
+++ b/sys/src/9/bcm64/trap.c
@@ -10,6 +10,8 @@
#include "ureg.h"
#include "sysreg.h"
+int (*buserror)(Ureg*);
+
/* SPSR bits user can modify */
#define USPSRMASK (0xFULL<<28)
@@ -141,6 +143,8 @@
}
if(intr == 3){case 0x2F: // SError interrupt
+ if(buserror != nil && (*buserror)(ureg))
+ break;
dumpregs(ureg);
panic("SError interrupt");break;