shithub: riscv

ref: 17f7f6be4e1a316c0f5f26ff70e047aece4de2bc
dir: /sys/src/ape/lib/ap/arm64/cycles.s/

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#define	SYSREG(op0,op1,Cn,Cm,op2)	SPR(((op0)<<19|(op1)<<16|(Cn)<<12|(Cm)<<8|(op2)<<5))
#define CNTVCT_EL0			SYSREG(3,3,14,0,2)

TEXT _cycles(SB), 1, $-4
	MRS	CNTVCT_EL0, R1
	MOV	R1, (R0)
	RETURN