ref: 1a5c8430d20d7ec5cd52c8335af6490ab1dabcf2
parent: 8d16e980c29535d9d92a4a297077a51207cf93e4
author: cinap_lenrek <[email protected]>
date: Sun Dec 6 15:52:15 EST 2015
libmp: fix wrong move instruction for arm vector operations
--- a/sys/src/libmp/arm/mpvecadd.s
+++ b/sys/src/libmp/arm/mpvecadd.s
@@ -9,12 +9,12 @@
B.EQ _add1
SUB R6, R4, R4
_addloop1:
- MOVW.WP 4(R0), R1
- MOVW.WP 4(R5), R2
+ MOVW.P 4(R0), R1
+ MOVW.P 4(R5), R2
CMP $1, R3
ADC.S R2, R1
ADC R8, R8, R3
- MOVW.WP R1, 4(R7)
+ MOVW.P R1, 4(R7)
SUB.S $1, R6
B.NE _addloop1
_add1:
@@ -21,10 +21,10 @@
CMP R8, R4
B.EQ _addend
_addloop2:
- MOVW.WP 4(R0), R1
+ MOVW.P 4(R0), R1
ADD.S R3, R1
ADC R8, R8, R3
- MOVW.WP R1, 4(R7)
+ MOVW.P R1, 4(R7)
SUB.S $1, R4
B.NE _addloop2
_addend:
--- a/sys/src/libmp/arm/mpvecdigmuladd.s
+++ b/sys/src/libmp/arm/mpvecdigmuladd.s
@@ -5,12 +5,12 @@
MOVW $0, R2
_muladdloop:
MOVW $0, R1
- MOVW.WP 4(R0), R3
+ MOVW.P 4(R0), R3
MULALU R3, R5, (R1, R2)
MOVW (R6), R7
ADD.S R2, R7
ADC $0, R1, R2
- MOVW.WP R7, 4(R6)
+ MOVW.P R7, 4(R6)
SUB.S $1, R4
B.NE _muladdloop
MOVW (R6), R7
--- a/sys/src/libmp/arm/mpvecdigmulsub.s
+++ b/sys/src/libmp/arm/mpvecdigmulsub.s
@@ -5,13 +5,13 @@
MOVW $0, R2
_mulsubloop:
MOVW $0, R1
- MOVW.WP 4(R0), R3
+ MOVW.P 4(R0), R3
MULALU R3, R5, (R1, R2)
MOVW (R6), R7
SUB.S R2, R7
ADD.CC $1, R1
MOVW R1, R2
- MOVW.WP R7, 4(R6)
+ MOVW.P R7, 4(R6)
SUB.S $1, R4
B.NE _mulsubloop
MOVW (R6), R7
--- a/sys/src/libmp/arm/mpvecsub.s
+++ b/sys/src/libmp/arm/mpvecsub.s
@@ -9,12 +9,12 @@
B.EQ _sub1
SUB R6, R4, R4
_subloop1:
- MOVW.WP 4(R0), R1
- MOVW.WP 4(R5), R2
+ MOVW.P 4(R0), R1
+ MOVW.P 4(R5), R2
CMP R3, R8
SBC.S R2, R1
SBC R8, R8, R3
- MOVW.WP R1, 4(R7)
+ MOVW.P R1, 4(R7)
SUB.S $1, R6
B.NE _subloop1
_sub1:
@@ -21,11 +21,11 @@
CMP R8, R4
RET.EQ
_subloop2:
- MOVW.WP 4(R0), R1
+ MOVW.P 4(R0), R1
CMP R3, R8
SBC.S R8, R1
SBC R8, R8, R3
- MOVW.WP R1, 4(R7)
+ MOVW.P R1, 4(R7)
SUB.S $1, R4
B.NE _subloop2
RET