shithub: riscv

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ref: 49cd794fbdd661e8035eee41d053fedc30a5e165
parent: 752ba45fbf0d9122dd38e516bd7d2993b9210ff2
author: cinap_lenrek <[email protected]>
date: Fri Jul 8 00:16:37 EDT 2016

5l: ROR instruction

--- a/sys/src/cmd/5l/asm.c
+++ b/sys/src/cmd/5l/asm.c
@@ -1522,6 +1522,7 @@
 	case ASLL:	return o | (0xd<<21) | (0<<5);
 	case ASRL:	return o | (0xd<<21) | (1<<5);
 	case ASRA:	return o | (0xd<<21) | (2<<5);
+	case AROR:	return o | (0xd<<21) | (3<<5);
 	case ASWI:	return o | (0xf<<24);
 
 	/* old arm 7500 fp using coproc 1 (1<<8) */
--- a/sys/src/cmd/5l/sched.c
+++ b/sys/src/cmd/5l/sched.c
@@ -288,6 +288,7 @@
 	case ASLL:
 	case ASRA:
 	case ASRL:
+	case AROR:
 	case ASUB:
 	case AEOR:
 
--- a/sys/src/cmd/5l/span.c
+++ b/sys/src/cmd/5l/span.c
@@ -726,6 +726,7 @@
 		case ASLL:
 			oprange[ASRL] = oprange[r];
 			oprange[ASRA] = oprange[r];
+			oprange[AROR] = oprange[r];
 			break;
 		case AMUL:
 			oprange[AMULU] = oprange[r];