ref: 7fd7d627e565b624e9cc1fecd837deb82f035d33
parent: 423b54a0aeea198c8d4c0cbb23a17236d68910ec
author: Sigrid Solveig Haflínudóttir <[email protected]>
date: Mon Aug 15 19:42:15 EDT 2022
imx8: enable/expose tmu
--- a/sys/src/9/imx8/ccm.c
+++ b/sys/src/9/imx8/ccm.c
@@ -760,6 +760,8 @@
{ "pcie_mem.mstr_axi_clk", MAIN_AXI_CLK_ROOT, 37 },
{ "pcie_mem.slv_axi_clk", MAIN_AXI_CLK_ROOT, 37 },
+ { "tmu.clk", IPG_CLK_ROOT, 98 },
+
{ "pcie2_clk_rst.auxclk", PCIE2_AUX_CLK_ROOT, 100 },
{ "pcie2_clk_rst.mstr_axi_clk", MAIN_AXI_CLK_ROOT, 100 },
{ "pcie2_clk_rst.slv_axi_clk", MAIN_AXI_CLK_ROOT, 100 },
--- a/sys/src/9/imx8/main.c
+++ b/sys/src/9/imx8/main.c
@@ -251,6 +251,20 @@
iprint("cpu%d: %dMHz ARM Cortex A53\n", m->machno, m->cpumhz);
}
+static void
+tmuinit(void)
+{
+ Physseg seg;
+
+ setclkgate("tmu.clk", 1);
+ memset(&seg, 0, sizeof(seg));
+ seg.attr = SG_PHYSICAL | SG_DEVICE | SG_NOEXEC;
+ seg.name = "tmu";
+ seg.pa = VIRTIO + 0x260000 - KZERO;
+ seg.size = BY2PG;
+ addphysseg(&seg);
+}
+
void
main(void)
{
@@ -289,6 +303,7 @@
links();
chandevreset();
lcdinit();
+ tmuinit();
userinit();
mpinit();
mmu0clear((uintptr*)L1);