shithub: riscv

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ref: 8c358c3f97db172a131c36d593b9aabeed6bc645
parent: faae8eb752fc9df65811ffb1b8cb8f0594cd4b2f
author: qwx <devnull@localhost>
date: Sun Aug 20 09:47:01 EDT 2017 

igfx: fix sandybridge fdi link training bits and ordering

- fix wrong bitfield for txctl (different between snb and ivb),
  and enable tx before rx
- DPLL_CTL_x snb/ivb: don't touch reserved bits


--- a/sys/src/cmd/aux/vga/igfx.c
+++ b/sys/src/cmd/aux/vga/igfx.c
@@ -869,7 +869,8 @@
 		dpll->ctrl.v &= ~(1<<30);
 
 	/* VGA Mode Disable */
-	dpll->ctrl.v |= (1<<28);
+	if(igfx->type == TypeG45)
+		dpll->ctrl.v |= (1<<28);
 
 	dpll->fp0.v &= ~(0x3f<<16);
 	dpll->fp0.v |= n << 16;
@@ -1394,7 +1395,11 @@
 		p->fdi->rxctl.v |= (1<<4);	/* pcdclk */
 		loadreg(igfx, p->fdi->rxctl);
 		sleep(5);
-		p->fdi->txctl.v &= ~(7<<8 | 1);	/* clear auto training bits */
+		/* clear auto training bits */
+		if(igfx->type == TypeSNB)
+			p->fdi->txctl.v &= ~(3<<28 | 1<<10 | 1);
+		else
+			p->fdi->txctl.v &= ~(7<<8 | 1);
 		p->fdi->txctl.v &= ~(1<<31);	/* disable */
 		p->fdi->txctl.v |= (1<<14);	/* enable pll */
 		loadreg(igfx, p->fdi->txctl);
@@ -1449,14 +1454,14 @@
 			/* unmask bit lock and symbol lock bits */
 			csr(igfx, p->fdi->rximr.a, 3<<8, 0);
 
+			p->fdi->txctl.v &= ~(3<<28);	/* link train pattern1 */
+			p->fdi->txctl.v |= 1<<31;	/* enable */
+			loadreg(igfx, p->fdi->txctl);
+
 			p->fdi->rxctl.v &= ~(3<<8);	/* link train pattern1 */
 			p->fdi->rxctl.v |= 1<<31;	/* enable */
 			loadreg(igfx, p->fdi->rxctl);
 
-			p->fdi->txctl.v &= ~(3<<8);	/* link train pattern1 */
-			p->fdi->txctl.v |= 1<<31;	/* enable */
-			loadreg(igfx, p->fdi->txctl);
-
 			/* wait for bit lock */
 			for(i=0; i<10; i++){
 				sleep(1);
@@ -1466,8 +1471,8 @@
 			csr(igfx, p->fdi->rxiir.a, 0, 1<<8);
 	
 			/* switch to link train pattern2 */
+			csr(igfx, p->fdi->txctl.a, 3<<28, 1<<28);
 			csr(igfx, p->fdi->rxctl.a, 3<<8, 1<<8);
-			csr(igfx, p->fdi->txctl.a, 3<<8, 1<<8);
 
 			/* wait for symbol lock */
 			for(i=0; i<10; i++){
@@ -1478,8 +1483,8 @@
 			csr(igfx, p->fdi->rxiir.a, 0, 1<<9);
 
 			/* switch to link train normal */
+			csr(igfx, p->fdi->txctl.a, 0, 3<<28);
 			csr(igfx, p->fdi->rxctl.a, 0, 3<<8);
-			csr(igfx, p->fdi->txctl.a, 0, 3<<8);
 
 			/* wait idle pattern time */
 			sleep(5);