ref: 90f47fadf8808d84d9bde8316f3945e60650093d
parent: 2b89cdee025d9b3faccd62bc3515d7ed749ae26f
author: cinap_lenrek <[email protected]>
date: Sat Jul 9 12:06:42 EDT 2022
imx8: detect cpu lcycles() frequency
--- a/sys/src/9/imx8/clock.c
+++ b/sys/src/9/imx8/clock.c
@@ -29,6 +29,9 @@
void
clockinit(void)
{
+ uvlong tstart, tend;
+ ulong t0, t1;
+
syswr(PMCR_EL0, 1<<6 | 7);
syswr(PMCNTENSET, 1<<31);
syswr(PMUSERENR_EL0, 1<<2);
@@ -41,8 +44,22 @@
freq = sysrd(CNTFRQ_EL0);
print("timer frequency %lld Hz\n", freq);
}
- m->cpuhz = freq;
- m->cpumhz = (freq + Mhz/2 - 1) / Mhz;
+ tstart = sysrd(CNTPCT_EL0);
+ do{
+ t0 = lcycles();
+ }while(sysrd(CNTPCT_EL0) == tstart);
+ tend = tstart + (freq/100);
+ do{
+ t1 = lcycles();
+ }while(sysrd(CNTPCT_EL0) < tend);
+ t1 -= t0;
+ m->cpuhz = 100 * t1;
+ m->cpumhz = (m->cpuhz + Mhz/2 - 1) / Mhz;
+
+ /*
+ * we are using virtual counter register CNTVCT_EL0
+ * instead of the performance counter in userspace.
+ */
m->cyclefreq = freq;
intrenable(IRQcntpns, localclockintr, nil, BUSUNKNOWN, "clock");
--- a/sys/src/9/imx8/main.c
+++ b/sys/src/9/imx8/main.c
@@ -135,6 +135,12 @@
}
void
+cpuidprint(void)
+{
+ iprint("cpu%d: %dMHz ARM Cortex A53\n", m->machno, m->cpumhz);
+}
+
+void
main(void)
{
machinit();
@@ -143,6 +149,7 @@
fpuinit();
intrinit();
clockinit();
+ cpuidprint();
synccycles();
timersinit();
flushtlb();
@@ -162,6 +169,7 @@
fpuinit();
intrinit();
clockinit();
+ cpuidprint();
timersinit();
pageinit();
procinit0();