shithub: riscv

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--- a/sys/src/9/pc/memory.c

+++ b/sys/src/9/pc/memory.c

@@ -383,16 +383,8 @@

 		}

 	}

-	/*

-	 * Make sure RAM is set to writeback,

-	 * but do a sanity check first checking

-	 * that the kernel text is writeback.

-	 * This is needed as some emulators (bhyve)

-	 * set everything to uncached.

-	 */

-	s = mtrrattr(PADDR(KTZERO), nil);

-	if(s != nil && strcmp(s, "wb") == 0)

-		mtrrexclude(MemRAM, "wb");

+	/* RAM needs to be writeback */

+	mtrrexclude(MemRAM, "wb");

 	for(base = memmapnext(-1, MemRAM); base != -1; base = memmapnext(base, MemRAM)){

 		size = memmapsize(base, BY2PG) & ~(BY2PG-1);

--- a/sys/src/9/pc/mtrr.c

+++ b/sys/src/9/pc/mtrr.c

@@ -305,12 +305,14 @@

 	vlong v;

 	int i;

-	s->mask = physmask();

+	if(rdmsr(MTRRCap, &s->cap) < 0)

+		return -1;

+	if((s->cap & (Capfix|Capvcnt)) == 0)

+		return -1;

+

 	if(rdmsr(MTRRDefaultType, &s->def) < 0)

 		return -1;

-	if(rdmsr(MTRRCap, &s->cap) < 0)

-		return -1;

 	if(s->cap & Capfix){

 		for(i = 0; i < nelem(fixreg); i++){

@@ -332,6 +334,8 @@

 			return -1;

 	}

+	s->mask = physmask();

+

 	if(strcmp(m->cpuidid, "AuthenticAMD") != 0

 	|| m->cpuidfamily < 15

 	|| rdmsr(AMDK8SysCfg, &v) < 0

@@ -673,6 +677,10 @@

 	new.size = size;

 	if((new.type = str2type(tstr)) < 0)

 		return "bad cache type";

+

+	if(new.type == Writecomb

+	&& (cpu0state.cap & Capwc) == 0)

+		return "write combining not supported";

 	qlock(&mtrrlk);

 	newstate = cpu0state;