ref: eaf799e8c4e25df6953046544ec5ef5e36fc921a
parent: 6723fdf7b7c7fc3231bb1868139c768301ff03b9
author: Sigrid Solveig Haflínudóttir <[email protected]>
date: Wed May 10 16:57:17 EDT 2023
libmach/acid: add basic FP support for arm64
--- a/sys/lib/acid/arm64
+++ b/sys/lib/acid/arm64
@@ -48,6 +48,43 @@
print("R30\t", *R30, "\n");}
+defn fprF()
+{+ print("FPSR ", *FPSR, " FPCR ", *FPCR, "\n");+ print("F0\t", *F0, " F1\t", *F1, " F2\t", *F2, "\n");+ print("F3\t", *F3, " F4\t", *F4, " F5\t", *F5, "\n");+ print("F6\t", *F6, " F7\t", *F7, " F8\t", *F8, "\n");+ print("F9\t", *F9, " F10\t", *F10, " F11\t", *F11, "\n");+ print("F12\t", *F12, " F13\t", *F13, " F14\t", *F14, "\n");+ print("F15\t", *F15, " F16\t", *F16, " F17\t", *F17, "\n");+ print("F18\t", *F18, " F19\t", *F19, " F20\t", *F20, "\n");+ print("F21\t", *F21, " F22\t", *F22, " F23\t", *F23, "\n");+ print("F24\t", *F24, " F25\t", *F25, " F26\t", *F26, "\n");+ print("F27\t", *F27, " F28\t", *F28, " F29\t", *F29, "\n");+ print("F30\t", *F30, " F31\t", *F31, "\n");+}
+
+defn fprf()
+{+ print("FPSR ", *FPSR, " FPCR ", *FPCR, "\n");+ print("f0\t", *f0, " f1\t", *f1, " f2\t", *f2, "\n");+ print("f3\t", *f3, " f4\t", *f4, " f5\t", *f5, "\n");+ print("f6\t", *f6, " f7\t", *f7, " f8\t", *f8, "\n");+ print("f9\t", *f9, " f10\t", *f10, " f11\t", *f11, "\n");+ print("f12\t", *f12, " f13\t", *f13, " f14\t", *f14, "\n");+ print("f15\t", *f15, " f16\t", *f16, " f17\t", *f17, "\n");+ print("f18\t", *f18, " f19\t", *f19, " f20\t", *f20, "\n");+ print("f21\t", *f21, " f22\t", *f22, " f23\t", *f23, "\n");+ print("f24\t", *f24, " f25\t", *f25, " f26\t", *f26, "\n");+ print("f27\t", *f27, " f28\t", *f28, " f29\t", *f29, "\n");+ print("f30\t", *f30, " f31\t", *f31, "\n");+}
+
+defn fpr()
+{+ fprF();
+}
+
defn regs() // print all registers
{gpr();
--- a/sys/src/libmach/7.c
+++ b/sys/src/libmach/7.c
@@ -8,13 +8,16 @@
#include "/arm64/include/ureg.h"
+#define REGSIZE sizeof(struct Ureg)
+#define FPREGSIZE 520
+
#define REGOFF(x) (uintptr)(&((struct Ureg *) 0)->x)
+#define FP_REG(x) (REGSIZE+16*(x))
+#define FP_CTL(x) (FP_REG(32)+4*(x))
#define SP REGOFF(sp)
#define PC REGOFF(pc)
-#define REGSIZE sizeof(struct Ureg)
-
Reglist arm64reglist[] =
{ {"TYPE", REGOFF(type), RINT|RRDONLY, 'Y'},@@ -52,6 +55,75 @@
{"R2", REGOFF(r2), RINT, 'Y'}, {"R1", REGOFF(r1), RINT, 'Y'}, {"R0", REGOFF(r0), RINT, 'Y'},+
+ {"FPSR", FP_CTL(1), RINT, 'X'},+ {"FPCR", FP_CTL(0), RINT, 'X'},+
+ {"F31", FP_REG(31), RFLT, 'F'}, /* double */+ {"F30", FP_REG(30), RFLT, 'F'},+ {"F29", FP_REG(29), RFLT, 'F'},+ {"F28", FP_REG(28), RFLT, 'F'},+ {"F27", FP_REG(27), RFLT, 'F'},+ {"F26", FP_REG(26), RFLT, 'F'},+ {"F25", FP_REG(25), RFLT, 'F'},+ {"F24", FP_REG(24), RFLT, 'F'},+ {"F23", FP_REG(23), RFLT, 'F'},+ {"F22", FP_REG(22), RFLT, 'F'},+ {"F21", FP_REG(21), RFLT, 'F'},+ {"F20", FP_REG(20), RFLT, 'F'},+ {"F19", FP_REG(19), RFLT, 'F'},+ {"F18", FP_REG(18), RFLT, 'F'},+ {"F17", FP_REG(17), RFLT, 'F'},+ {"F16", FP_REG(16), RFLT, 'F'},+ {"F15", FP_REG(15), RFLT, 'F'},+ {"F14", FP_REG(14), RFLT, 'F'},+ {"F13", FP_REG(13), RFLT, 'F'},+ {"F12", FP_REG(12), RFLT, 'F'},+ {"F11", FP_REG(11), RFLT, 'F'},+ {"F10", FP_REG(10), RFLT, 'F'},+ {"F9", FP_REG(9), RFLT, 'F'},+ {"F8", FP_REG(8), RFLT, 'F'},+ {"F7", FP_REG(7), RFLT, 'F'},+ {"F6", FP_REG(6), RFLT, 'F'},+ {"F5", FP_REG(5), RFLT, 'F'},+ {"F4", FP_REG(4), RFLT, 'F'},+ {"F3", FP_REG(3), RFLT, 'F'},+ {"F2", FP_REG(2), RFLT, 'F'},+ {"F1", FP_REG(1), RFLT, 'F'},+ {"F0", FP_REG(0), RFLT, 'F'},+
+ {"f31", FP_REG(31), RFLT, 'f'}, /* double */+ {"f30", FP_REG(30), RFLT, 'f'},+ {"f29", FP_REG(29), RFLT, 'f'},+ {"f28", FP_REG(28), RFLT, 'f'},+ {"f27", FP_REG(27), RFLT, 'f'},+ {"f26", FP_REG(26), RFLT, 'f'},+ {"f25", FP_REG(25), RFLT, 'f'},+ {"f24", FP_REG(24), RFLT, 'f'},+ {"f23", FP_REG(23), RFLT, 'f'},+ {"f22", FP_REG(22), RFLT, 'f'},+ {"f21", FP_REG(21), RFLT, 'f'},+ {"f20", FP_REG(20), RFLT, 'f'},+ {"f19", FP_REG(19), RFLT, 'f'},+ {"f18", FP_REG(18), RFLT, 'f'},+ {"f17", FP_REG(17), RFLT, 'f'},+ {"f16", FP_REG(16), RFLT, 'f'},+ {"f15", FP_REG(15), RFLT, 'f'},+ {"f14", FP_REG(14), RFLT, 'f'},+ {"f13", FP_REG(13), RFLT, 'f'},+ {"f12", FP_REG(12), RFLT, 'f'},+ {"f11", FP_REG(11), RFLT, 'f'},+ {"f10", FP_REG(10), RFLT, 'f'},+ {"f9", FP_REG(9), RFLT, 'f'},+ {"f8", FP_REG(8), RFLT, 'f'},+ {"f7", FP_REG(7), RFLT, 'f'},+ {"f6", FP_REG(6), RFLT, 'f'},+ {"f5", FP_REG(5), RFLT, 'f'},+ {"f4", FP_REG(4), RFLT, 'f'},+ {"f3", FP_REG(3), RFLT, 'f'},+ {"f2", FP_REG(2), RFLT, 'f'},+ {"f1", FP_REG(1), RFLT, 'f'},+ {"f0", FP_REG(0), RFLT, 'f'}, { 0 }};
@@ -62,7 +134,7 @@
MARM64, /* machine type */
arm64reglist, /* register set */
REGSIZE, /* register set size */
- 0, /* fp register set size */
+ FPREGSIZE, /* fp register set size */
"PC", /* name of PC */
"SP", /* name of SP */
"R30", /* name of link register */
--- a/sys/src/libmach/7db.c
+++ b/sys/src/libmach/7db.c
@@ -49,8 +49,8 @@
riscframe, /* Frame finder */
arm64excep, /* print exception */
0, /* breakpoint fixup */
- 0, /* single precision float printer */
- 0, /* double precision float printer */
+ leieeesftos, /* single precision float printer */
+ leieeedftos, /* double precision float printer */
arm64foll, /* following addresses */
arm64inst, /* print instruction */
arm64das, /* dissembler */
@@ -258,6 +258,12 @@
"11010101000000110100xxxx11111111", "MSR", "$%x,DAIFClr",
"11010101000YYYYYYYYYYYYYYYYddddd", "MSR", "R%d,%Y",
"11010101001YYYYYYYYYYYYYYYYddddd", "MRS", "%Y,R%d",
+ "FF11110101uuuuuuuuuuuu11111ddddd", "FMOV%F", "%u(SP),F%d",
+ "FF11110101uuuuuuuuuuuunnnnnddddd", "FMOV%F", "%u(R%n),F%d",
+ "FF111100010ooooooooo0011111ddddd", "FMOV%F", "%o(SP),F%d",
+ "FF111100010ooooooooo00nnnnnddddd", "FMOV%F", "%o(R%n),F%d",
+ "W0011110ZZ111000000000nnnnnddddd", "FCVTZS%Z%W", "F%n,R%d",
+ "W0011110ZZ111001000000nnnnnddddd", "FCVTZU%Z%W", "F%n,R%d",
"xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx", "WORD", "$%x",
};
@@ -471,6 +477,11 @@
*i->curr++ = "BHW"[u];
break;
+ case 'F': // FP width
+ u &= 3;
+ *i->curr++ = "BHSD"[u];
+ break;
+
case 'd': // Register Numbers
case 'n':
case 'a':
@@ -590,6 +601,10 @@
case SYSARG5(3,0,4,2,0): bprint(i, "SPSel"); break;
default: bprint(i, "SPR(%lux)", i->w & m);
}
+ break;
+
+ case 'Z': // FP type
+ *i->curr++ = "SD?H"[u];
break;
case '\0':