ref: 0237b583906353b78f9cbf2194dc083e82b8ba23
dir: /sys/lib/acid/alpha/
// Alpha support defn acidinit() // Called after all the init modules are loaded { bplist = {}; bpfmt = 'X'; srcpath = { "./", "/sys/src/libc/port/", "/sys/src/libc/9sys/", "/sys/src/libc/alpha/" }; srcfiles = {}; // list of loaded files srctext = {}; // the text of the files } defn stk() // trace { _stk(*PC, *SP, linkreg(0), 0); } defn lstk() // trace with locals { _stk(*PC, *SP, linkreg(0), 1); } defn gpr() // print general purpose registers { print("R0\t", *R0, "\n"); print("R1\t", *R1, " R2\t", *R2, " R3\t", *R3, "\n"); print("R4\t", *R4, " R5\t", *R5, " R6\t", *R6, "\n"); print("R7\t", *R7, " R8\t", *R8, " R9\t", *R9, "\n"); print("R10\t", *R10, " R11\t", *R11, " R12\t", *R12, "\n"); print("R13\t", *R13, " R14\t", *R14, " R15\t", *R15, "\n"); print("R16\t", *R16, " R17\t", *R17, " R18\t", *R18, "\n"); print("R19\t", *R19, " R20\t", *R20, " R21\t", *R21, "\n"); print("R22\t", *R22, " R23\t", *R23, " R24\t", *R24, "\n"); print("R25\t", *R25, " R26\t", *R26, " R27\t", *R27, "\n"); print("R28\t", *R28, " R29\t", *R29, " R30\t", *SP\Y, "\n"); } defn fpr() { print("F0\t", *fmt(F0, 'G'), "\tF1\t", *fmt(F1, 'G'), "\n"); print("F2\t", *fmt(F2, 'G'), "\tF3\t", *fmt(F3, 'G'), "\n"); print("F4\t", *fmt(F4, 'G'), "\tF5\t", *fmt(F5, 'G'), "\n"); print("F6\t", *fmt(F6, 'G'), "\tF7\t", *fmt(F7, 'G'), "\n"); print("F8\t", *fmt(F8, 'G'), "\tF9\t", *fmt(F9, 'G'), "\n"); print("F10\t", *fmt(F10, 'G'), "\tF11\t", *fmt(F11, 'G'), "\n"); print("F12\t", *fmt(F12, 'G'), "\tF13\t", *fmt(F13, 'G'), "\n"); print("F14\t", *fmt(F14, 'G'), "\tF15\t", *fmt(F15, 'G'), "\n"); print("F16\t", *fmt(F16, 'G'), "\tF17\t", *fmt(F17, 'G'), "\n"); print("F18\t", *fmt(F18, 'G'), "\tF19\t", *fmt(F19, 'G'), "\n"); print("F20\t", *fmt(F20, 'G'), "\tF21\t", *fmt(F21, 'G'), "\n"); print("F22\t", *fmt(F22, 'G'), "\tF23\t", *fmt(F23, 'G'), "\n"); print("F24\t", *fmt(F24, 'G'), "\tF25\t", *fmt(F25, 'G'), "\n"); print("F26\t", *fmt(F26, 'G'), "\tF27\t", *fmt(F27, 'G'), "\n"); print("F28\t", *fmt(F28, 'G'), "\tF29\t", *fmt(F29, 'G'), "\n"); print("F30\t", *fmt(F30, 'G'), "\tF31\t", *fmt(F31, 'G'), "\n"); } defn spr() // print special processor registers { local pc, link, cause; pc = *PC; print("PC\t", pc, " ", fmt(pc, 'a'), " "); pfl(pc); link = *R26; print("SP\t", *SP, "\tLINK\t", link, " ", fmt(link, 'a'), " "); pfl(link); cause = *TYPE; print("STATUS\t", *STATUS, "\tTYPE\t", cause, " ", reason(cause), "\n"); print("A0\t", *A0, " A1\t", *A1, " A2\t", *A2, "\n"); } defn regs() // print all registers { spr(); gpr(); } defn pstop(pid) { local l, pc; pc = *PC; print(pid,": ", reason(*TYPE), "\t"); print(fmt(pc, 'a'), "\t", fmt(pc, 'i'), "\n"); if notes then { if notes[0] != "sys: breakpoint" then { print("Notes pending:\n"); l = notes; while l do { print("\t", head l, "\n"); l = tail l; } } } } sizeofUreg = 296; aggr Ureg { 'W' 0 type; 'W' 8 a0; 'W' 16 a1; 'W' 24 a2; 'W' 32 r0; 'W' 40 r1; 'W' 48 r2; 'W' 56 r3; 'W' 64 r4; 'W' 72 r5; 'W' 80 r6; 'W' 88 r7; 'W' 96 r8; 'W' 104 r9; 'W' 112 r10; 'W' 120 r11; 'W' 128 r12; 'W' 136 r13; 'W' 144 r14; 'W' 152 r15; 'W' 160 r19; 'W' 168 r20; 'W' 176 r21; 'W' 184 r22; 'W' 192 r23; 'W' 200 r24; 'W' 208 r25; 'W' 216 r26; 'W' 224 r27; 'W' 232 r28; { 'W' 240 r30; 'W' 240 usp; 'W' 240 sp; }; 'W' 248 status; 'W' 256 pc; 'W' 264 r29; 'W' 272 r16; 'W' 280 r17; 'W' 288 r18; }; defn Ureg(addr) { complex Ureg addr; print(" type ", addr.type, "\n"); print(" a0 ", addr.a0, "\n"); print(" a1 ", addr.a1, "\n"); print(" a2 ", addr.a2, "\n"); print(" r0 ", addr.r0, "\n"); print(" r1 ", addr.r1, "\n"); print(" r2 ", addr.r2, "\n"); print(" r3 ", addr.r3, "\n"); print(" r4 ", addr.r4, "\n"); print(" r5 ", addr.r5, "\n"); print(" r6 ", addr.r6, "\n"); print(" r7 ", addr.r7, "\n"); print(" r8 ", addr.r8, "\n"); print(" r9 ", addr.r9, "\n"); print(" r10 ", addr.r10, "\n"); print(" r11 ", addr.r11, "\n"); print(" r12 ", addr.r12, "\n"); print(" r13 ", addr.r13, "\n"); print(" r14 ", addr.r14, "\n"); print(" r15 ", addr.r15, "\n"); print(" r19 ", addr.r19, "\n"); print(" r20 ", addr.r20, "\n"); print(" r21 ", addr.r21, "\n"); print(" r22 ", addr.r22, "\n"); print(" r23 ", addr.r23, "\n"); print(" r24 ", addr.r24, "\n"); print(" r25 ", addr.r25, "\n"); print(" r26 ", addr.r26, "\n"); print(" r27 ", addr.r27, "\n"); print(" r28 ", addr.r28, "\n"); print("_12_ {\n"); _12_(addr+240); print("}\n"); print(" status ", addr.status, "\n"); print(" pc ", addr.pc, "\n"); print(" r29 ", addr.r29, "\n"); print(" r16 ", addr.r16, "\n"); print(" r17 ", addr.r17, "\n"); print(" r18 ", addr.r18, "\n"); }; defn linkreg(addr) { complex Ureg addr; return addr.r26\X; } print("/sys/lib/acid/alpha");