shithub: riscv

ref: 5f7a6b7ea3c4ae1b51beffe3309e9b6b0491e71f
dir: /sys/src/libc/arm64/cycles.s/

View raw version 
#define	SYSREG(op0,op1,Cn,Cm,op2)	SPR(((op0)<<19|(op1)<<16|(Cn)<<12|(Cm)<<8|(op2)<<5))
#define PMCCNTR_EL0			SYSREG(3,3,9,13,0)

TEXT cycles(SB), 1, $-4
	MRS	PMCCNTR_EL0, R1
	MOV	R1, (R0)
	RETURN